Atmel /AT91SAM9G20 /SPI0 /CSR[1]

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CSR[1]

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CPOL)CPOL 0 (NCPHA)NCPHA 0 (CSAAT)CSAAT 0 (8_BIT)BITS0SCBR0DLYBS0DLYBCT

BITS=8_BIT

Description

Chip Select Register

Fields

CPOL

Clock Polarity

NCPHA

Clock Phase

CSAAT

Chip Select Active After Transfer

BITS

Bits Per Transfer

0 (8_BIT): 8 bits for transfer

1 (9_BIT): 9 bits for transfer

2 (10_BIT): 10 bits for transfer

3 (11_BIT): 11 bits for transfer

4 (12_BIT): 12 bits for transfer

5 (13_BIT): 13 bits for transfer

6 (14_BIT): 14 bits for transfer

7 (15_BIT): 15 bits for transfer

8 (16_BIT): 16 bits for transfer

SCBR

Serial Clock Baud Rate

DLYBS

Delay Before SPCK

DLYBCT

Delay Between Consecutive Transfers

Links

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